vlsi projects in chennai - VLSI Architecture of Arithmetic Coder Used in SPIHT

VLSI  Architecture of Arithmetic Coder Used in SPIHT

 

Proposed system:

          We propose a high speed architecture of  Arithmetic coder used in SPIHT without lists algorithm. Proposed architecture is concerned there are three stages during implementation. The first step for designing an AC in SPIHT is to set a context model suitable for hardware processing. One of context model is designed in the QccPack(Quantization, Compression, and Coding Library) SPIHT. In the architecture, a simple context model based on the QccPackSPIHT software is designed, which just exploits the relationship of nodes in one zero tree and establishes four types of context for current position value, current position sign, descendant set (D set) and grant descendant set (L set). The second step is to remove the internal loops of AC and arrange different modules for hardware. The last step is to connect all modules by different paths to build one AC.

2.2.1 Advantages:

Ø Reduce power consumption.

Ø We can stop some bit-plane coders by cutting its input clock according to the maximal coefficient in wavelet domain adaptively.

Ø High throughput.

2.3 Applications:

Ø Real time image compression applications such as Digital TV, Satellite communication.

Ø Compression of elevation maps, scientific data, and others.

Ø Its embedded coding process proved to be effective in a broad range of reconstruction qualities. For instance, it can code fair-quality portraits and high-quality medical images equally well (as compared with other methods in the same conditions).