ABSTRACT
Design
of memory in FPGA become mandatory in developing high speed technology.
Emerging non-volatile Magnetic Random
Access Memory (MRAM) is a promising alternative for replacement
of SRAM-based configuration bits of conventional FPGAs. However, the costs of
reconfiguration in MRAM-FPGAs are typically higher than SRAM-FPGAs due to the
high write latency and energy of MRAM. In the existing design, a novel
energy-efficient partitioning technique is proposed to minimize the number of
reconfigurations and content updates for dynamic reconfigurable MRAM-FPGAs. The
simulation results show that the proposed technique significantly reduces the
reconfiguration energy (up to 68.1% on average) as compared to the existing
partitioning techniques.
EXISTING SYSTEM
In
the existing design, a novel energy-efficient partitioning technique is
proposed to minimize the number of reconfigurations and content updates for
dynamic reconfigurable MRAM-FPGAs. The simulation results show that the
proposed technique significantly reduces the reconfiguration energy (up to
68.1% on average) as compared to the existing partitioning techniques.
PROPOSED SYSTEM
In
the proposed system a FPGA Mother board platform is designed using configurable
logic blocks. The platform enables the user to utilize required partitioning
for multiple applications in a single platform. Sometimes high speed of clock
switching can disturb the flow of operation too.So doing CLB partitioning
enable the design more flexible in changing the mode according to the
application. Power is utilized properly. Area utilization is done.
Advantages
of Proposed system
·
Area utilization done
·
Multiple operations in a single Block
·
Clock switching interfaces are reduced here.
Software
Required
·
Simulation : MODELSIM 6.3 G ALTERA
·
Implementation : XILINX ISE 10.5
·
Language : VHDL
·
Power : XILINX XPE
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