ieee projects in chennai - Active Filter-Based Hybrid on-Chip DC–DC Converter for Point-of-Load Voltage Regulation

Active Filter-Based Hybrid on-Chip DC–DC Converter for Point-of-Load Voltage Regulation

Abstract:-

The design of active filter-based on-chip DC–DC voltage converter is realized here for application to distributed on-chip power supplies in multi voltage systems is described in this paper. No inductor or output capacitor is required in the proposed converter. The area of the voltage converter is therefore significantly less than that of a conventional low-dropout regulator. Hence, the proposed circuit is appropriate for point-of-load voltage regulation for noise sensitive portions of an integrated circuit. In the present design the performance of the circuit has been verified with Cadence Spectre simulations and fabricated with a commercial 110 nm complimentary metal oxide semiconductor technology. The parameter sensitivity of the active filter is also described. The advantages and disadvantages of the active filter-based, conventional switching, linear, and switched capacitor voltage converters are compared. The proposed circuit is an alternative to classical LDO voltage regulators, providing a means for distributing multiple local power supplies across an integrated circuit while maintaining high current efficiency and  fast response time within a small area.

Existing System:-

In the existing design the active filter is implemented to build on chip DC DC Converter for voltage regulation. It shows that in the present design , On chip activities are routed through distribution networks, The maximum current that can be delivered to the load depends upon the size of the power transistors (PMOS and NMOS shown in Fig. 2) driving the LC filter. A higher current can be delivered with larger power transistors. The maximum load current of an LDO regulator depends upon the size of the pass transistor.

 

Proposed System:-            

In the proposed design the active filter concept is implemented and LDO dc dc conversion algorithm also being developed. The clock distribution network  also designed with signal analysis module to detect glitches in the Converted output.

 Software Requirements:-

Design Environment: XILINX ISE

Language: VHDL

Simulation : MODELSIM / XILINX ISE Simulator

Hardware Requirements:-

XILINX SPARTAN Development Board

Device : XC3S500E