Low-Energy N-Stage Algorithm for High Efficacy Epileptic Seizure Detection

 Design Description:

Design of EEG Signal detection:

This module consists of detection, reading of EEG values of the patients. A periodical data set is monitored and stored into a database. Digital modules read the file data and make it to processing or accessible format.

Design of COASTLINE algorithm

This module consists of detection stage consists of the DWTQA algorithm as was presented. The warning flag from the monitoring stage is used to activate the detection stage. The DWTQA takes the digitized input data and resolves them into narrow frequency bands in terms of wavelet coefficients. The wavelet chosen is Daubechies-4 (DB-4) due to its ability to capture the spiking and smoothening nature of the LFP. The patient-specific significant coefficients are quasi-averaged, weighted, and added over a prefixed window to produce the detection signal.

Design of DWT Module

The DWT block decomposes the signal into wavelet coefficients, each corresponding to a narrow frequency band, using the Mallet algorithm. The sample data required six such coefficients. The wavelet coefficients are computed using successive low and high pass filter (LPF and HPF) stages and intermediate down sampling. The DB-4 mother wavelet is used in the DWT block. We also explored the use of DB-2 and DB-6 wavelet and show the degradation in efficacy. The DB-4 can be represented in terms of HPF and LPF of eighth order. Low power techniques, such as computation sharing multiplier and common sub expression elimination, are utilized for their implementation. Using these techniques, the power intensive multipliers in filters are replaced with few shifts and add operations

Design of N-STAGE Controller:

This module consists of control signal generation used for the N-STAGE control which is used to reduce space and area utilization. The design of N-Stage provides re-configurable architecture.

Design of Integration Module:

This module consists of integration of all the sub modules in a Finite state machine method to run and detect the signals in a continuous manner until the system clock comes

Algorithm Flow

 

PROPOSED BLOCK DIAGRAM

 

SIMULATION RESULT