The LUT-SR Family of Uniform Random
Number Generators for FPGA Architectures
EXISTING
SYSTEM:
Existing technology
proposed Linear Feedback Shift Register (LFSR) random number
generators, also called Tausworthe generators, are based on linear recurrences
modulo 2 with primitive characteristic polynomials. Efficient implementations
are available for the case where the characteristic polynomial is a trinomial
and satisfies some additional conditions. Trinomial-based generators have
important statistical defects, but combining them can yield generators that are
relatively fast and robust. it has been explained how to find combined
generators with the best possible equi distribution properties in some sense,
within specified classes of combined LFSR generators. Three specific combined
generators, each with three components and period length also given.
DISADVANTAGE OF EXISTING:
Ø Implementations
on FPGA limited by minimal delay.
Ø
Limte
the operation frequency.
Ø
Input
clock is made half the time dely to pass through the delay line.
The proposed architecture relies on
multiple parallel programmable delay lines implemented as a series of
programmable interconnection points. The realization of these delay lines is
presented in A precise adjustment of each delay can be made using dynamic
reconfiguration by modifying the routing of each interconnection. As this sort
of fine-grain adjustment is subject to process variations, a calibration process
that takes into account programmable interconnection points delay variations
and clock skew within the global distribution tree is also proposed.
2.2.ADVANTAGE
OF PROPOSED WORK:
Ø Fast
development process.
Ø Flexible
Clock frequency.
Ø
Greater design flexibility and reduced minimal
delays.
Ø
These proposed works achieve delay lines with a
1-ps resolution.
2.3
Applications:
Ø Laser
range finder.
Ø Testing
instrument.
Ø Radio
frequency.
Ø
Time-of-flight
mass spectrometry experiments.
Ø Positron
emission to mography for medical imaging.
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