VLSI
Design and implementation of Content address Memory with Reconfigurable Memory
banks
OBJECTIVE
To design a low power inputs configured
Content address memory with reconfigurable Memory banks.
SCOPE OF THE STUDY
- This study enables us to get in depth knowledge on how reconfigurable platforms are implemented in VLSI technology
- This study help us to learn about low power techniques such as clock gating and power gating etc
ABSTRACT
Content addressable memories (CAMs) compare search data against a table of stored data
and return the address of
the matched data (if any).
Traditional CAM
design has always suffered from the high dynamic power consumption associated with its large and active
parallel hardware. In the previous
design, they
explored
the design space of FinFET CAMs using
SG (fast, but leaky) and ASG FinFETs (slower, but much less leaky), and pro pose two new variants of CAM bitcells (All-ASG and Core-ASG). They evaluate several dc
metrics(read stability, write-ability, and leakage current) of CAM bitcells. They demonstrate the
importance of leakage in the total power of CAM array for
different mismatch probabilities.
They proposed
two mutually orthogonal layout strategies from a CAM array design perspective. We demonstrate that one layout style proves to be
superior to the other in transient
metrics (search delay and dynamic power) because of the large difference between their parasitic capacitances.
EXISTING SYSTEM
In existing,
they presented a layout-based
parasitic-aware design
space exploration of FinFET CAMs. The All-ASG bitcell was found to be superior to All-SG and and Core- ASG bitcells in terms of dc metrics. They observed that leakage power assumes slightly greater
significance with a decreasing mismatch
probability. ASG FinFETs play an important role in minimizing leakage in lower-mismatch cases. Finally, they observed noticeable
differences in parasitic capacitances between
two orthogonal layout styles (VSL and VML). VSL emerged as a better layout style in terms of dynamic energy and search delay because of its
inherent parasitic capacitance advantage.
DISADVANTAGES
1. Dynamic
power.
2. Leakage power slightly greater
PROPOSED SYSTEM
In
the proposed system, We are planning to design a high speed reconfigurable CAM.
Content address memory is nothing but the normal memory architecture in which
the logical modules enable the user to retrieve the information stored in the
memory within few nano seconds (few clock cycles ) through a systematic search
algorithm based on memory index data. The data stored in the memory under goes
a process of encryption before storing takes place. The data is purely packed
in the encryptor end where the data un-packed at the decryptor end as well. The
encrypted information is stored in the CAM. The data can be accessed using the
index bits for fast retrieval. The size of the memory banks can be varied with
respect to the low power reconfiguration bits available through a Switch
outside the FPGA. Hence some of low power techniques such as clock gating and
power gating is being used to improve the architecture performance in terms of
time.
ADVANTAGES
- Reconfigurable platform used for Multiple applications
- Single memory platform can be applied for multiple memory requirements
- Easily configured through I/O switches connected with FPGA
APPLICATIONS
1.
Local area
networks
2.
Database
management
3.
File-storage
management
4.
Pattern
recognition
5.
Artificial
intelligence
6.
Fully
associative and processor-specific cache memories
7.
Disk cache
memories
8.
Broadband
ATM communication system
9.
Image
coding
DESIGN DIAGRAM
SOFTWARE REQUIREMENT
Design Environment: XILINX ISE
Language: VHDL
Simulation: MODELSIM / XILINX ISE Simulator
Learning Continues
DivyaRamkumar
Sr.VLSI Design Engineer & Consultant
qmostech.com@gmail.com
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