phd projects in chennai : Time controlled behavioral FFT Architectures

Time controlled behavioral FFT Architectures

Objective:

      

     The objectives of this proposed architecture to design Pipelined Parallel FFT Architectures by using feed forward technique and register minimization techniques to reduce the power.

Existing system:

   In Existing technology much parallel architecture for FFT has been proposed. These  architectures are developed for a specific N-point FFT, whereas hypercube theory is used to derive the architectures  Radix-2 multi-path delay commutator (R2MDC) [5] is one of the most classical approaches for pipelined implementation of radix-2 FFT. Efficient usage of the storage buffer in R2MDC leads to the Radix-2 Single-path delay feedback (R2SDF) architecture with reduced memory. R4SDF  and R4MDC have been proposed as radix-4 versions of R2SDF and R4MDC, respectively. Radix-4 single-path delay commutator (R4SDC) is proposed using a modified radix-4 algorithm to reduce the complexity of the R4MDC architecture.

Disadvantage:

1. Ø Extra complexity would require for estimation.
   
   
   Ø  The algorithms are not well established.
   
   
   Ø  Most of these hardware architectures are not fully utilized.

 

Proposed System:

       Proposed technology presents a novel approach to design of  FFT architectures based on the Feed forward technique. In the folding transformation, many butterflies in the same column can be mapped to one butterfly unit. If the FFT size is , a folding factor of N/2 leads to a 2-parallel architecture. In another design, we can choose a folding factor of N/2 to design 4-parallel architectures, where four samples are processed in the same clock cycle. Different folding sets lead to a family of FFT architectures. Alternatively, known FFT architectures can also be described by the proposed methodology by selecting the appropriate folding set. Folding sets are designed intuitively to reduce latency and to reduce the number of storage elements. It may be noted that prior FFT architectures were derived in an adhoc way, and their derivations were not explained in a systematic way. This is the first attempt to generalize design of FFT architectures for arbitrary level of parallelism in a systematic manner via the folding transformation.

Advantages:

Ø  Reduce the number of storage elements.

Ø Achieve full hardware utilization.