Glitch-Free NAND-Based
Digitally Controlled
Delay-Lines
ABSTRACT
The
Combinational circuit which we designed was NAND-based digitally controlled delay-lines (DCDL)
present a glitching problem which may limit their employ in many applications.
This paper presents a glitch-free NAND-based DCDL which overcame this limitation by opening
the employ of NAND-based
DCDLs in a wide range of applications. The proposed NAND-based DCDL maintains the same
resolution and minimum delay of previously proposed NAND-based DCDL. The theoretical
demonstration of the glitch-free operation of proposed DCDL is also derived in
the paper. Following this analysis, three driving circuits for the delay
control-bits are also proposed. Proposed DCDLs have been designed in a 90-nm
CMOS technology and compared, in this technology, to the state-of-the-art.
Simulation results show that novel circuits result in the lowest resolution,
with a little worsening of the minimum delay with respect to the previously
proposed DCDL with the lowest delay. Simulations also confirm the correctness
of developed glitching model and sizing strategy. As example application, proposed
DCDL is used to realize an All-digital spread-spectrum clock generator (SSCG).
The employ of proposed DCDL in this circuit allows to reduce the peak-to-peak
absolute output jitter of more than the 40% with respect to a SSCG using
three-state inverter based DCDLs.
EXISTING SYSTEM
In
the existing design DCDLs have been designed in a 90-nm CMOS technology, to the
state-of-the-art. Simulation results show that novel circuits result in the
lowest resolution, with a little worsening of the minimum delay with respect to
the previously proposed DCDL with the lowest delay. We verify the logic in Simulations
itself which tells the correctness of developed glitching model and sizing
strategy. As example application, existing DCDL is used to realize an
All-digital spread-spectrum clock generator (SSCG). The employ of existing DCDL
in this circuit allows to reduce the peak-to-peak absolute output jitter of
more than the 40% with respect to a SSCG using three-state inverter based
DCDLs.
PROPOSED SYSTEM
In the proposed
system to avoid glitches and jitters occur during the fast switching operation
we introduce strobe controlled DCDL logic where each gate is under the control
of single strobe. Which reduces the error more than 50% comparing with the
previous method
SOFTWARE REQUIREMENT
Design
Environment: XILINX ISE
Language: VHDL
Simulation:
MODELSIM / XILINX ISE Simulator
HARDWARE REQUIREMENT
XILINX SPARTAN
Development Board
Device: XC3S500E
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