hi
I am sharing here a Logical idea to generate a 900 HZ frequency
please go through the VHDL code below and write to us if you need any support
VHDL CODE
Library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_bit.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_signed.all;
entity hz_90 is
port(clr: in std_logic;
inp_1ms:in std_logic;
hz_90_pulse:out std_logic);
end hz_90;
architecture behave of hz_90 is
-- 90 HZ Generation
signal cnt_90hz: integer;
signal dcod_90hz,clk_90hz: std_logic;
begin
--***************************************************
-- Process To count for 90 HZ
counter_90HZ:process(inp_1ms,clr)
begin
if clr='1' then
cnt_90hz<=0;
dcod_90hz<='0';
elsif rising_edge(inp_1ms) or falling_edge(inp_1ms) then
cnt_90hz<= cnt_90hz+1;
dcod_90hz<='0';
if cnt_90hz=10 then
cnt_90hz<=0;
dcod_90hz<='1';
end if;
end if;
end process counter_90HZ;
-- Generate 90 HZ pulse
clk_90HZs:process(dcod_90hz,clr)
begin
if clr='1' then
clk_90hz<='0';
elsif rising_edge(dcod_90hz) then
clk_90hz<= not clk_90hz;
end if;
end process clk_90HZs;
--***************************************************
-- DISPLAY OUTPUTS
hz_90_pulse <= clk_90hz;
end behave;
sIMULATION rESULTS
I am sharing here a Logical idea to generate a 900 HZ frequency
please go through the VHDL code below and write to us if you need any support
VHDL CODE
Library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_bit.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_signed.all;
entity hz_90 is
port(clr: in std_logic;
inp_1ms:in std_logic;
hz_90_pulse:out std_logic);
end hz_90;
architecture behave of hz_90 is
-- 90 HZ Generation
signal cnt_90hz: integer;
signal dcod_90hz,clk_90hz: std_logic;
begin
--***************************************************
-- Process To count for 90 HZ
counter_90HZ:process(inp_1ms,clr)
begin
if clr='1' then
cnt_90hz<=0;
dcod_90hz<='0';
elsif rising_edge(inp_1ms) or falling_edge(inp_1ms) then
cnt_90hz<= cnt_90hz+1;
dcod_90hz<='0';
if cnt_90hz=10 then
cnt_90hz<=0;
dcod_90hz<='1';
end if;
end if;
end process counter_90HZ;
-- Generate 90 HZ pulse
clk_90HZs:process(dcod_90hz,clr)
begin
if clr='1' then
clk_90hz<='0';
elsif rising_edge(dcod_90hz) then
clk_90hz<= not clk_90hz;
end if;
end process clk_90HZs;
--***************************************************
-- DISPLAY OUTPUTS
hz_90_pulse <= clk_90hz;
end behave;
sIMULATION rESULTS